1. Field
The present embodiments relate to a semiconductor memory.
2. Description of the Related Art
A semiconductor memory has a redundancy circuit in order to relieve defects caused by a lattice defect in a substrate and particles produced in a manufacture process and to improve the yield. A semiconductor memory such as a DRAM has a redundancy word line and a redundancy bit line in addition to a normal word line and bit line. When a defect of a memory cell is detected, a fuse circuit formed on the semiconductor memory is programmed in a test process in order to replace a defective word line or a defective bit line with the redundancy word line or the redundancy bit line. By relieving the defective memory cell using the redundancy circuit, the yield of the semiconductor memory is improved.
For instance, Japanese Laid-open Patent Publication No. 2003-7091 and the like disclose a method of making, when the single bit defect is generated due to the insufficiency of operation margin, normal memory cells defective using the LSI tester, until the single bit defect is determined as the bit line defect.